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		Algorithm Acceleration with Reconfigurable Hardware
			  LACSI Workshop, Oct. 11, 2005
			  Organizers: Maya B. Gokhale 
			  	      Rod R. Oldehoeft 
 
Over the past 15 years, direct execution of algorithms in
reconfigurable hardware has demonstrated speedup of one to two orders
of magnitude over equivalent software. Reconfigurable Computers (RC)
using Field Programmable Gate Arrays (FPGAs ) as processors have
emerged as co-processors to augment microprocessors in work stations,
clusters, and supercomputers. While RC offers remarkable opportunities
for performance, research challenges abound. The workshop will
be organized into two half-day sessions. The morning session will
present introductory topics and applications. The afternoon session
will include research topics in FPGA-based architectures, systems,
tools, and future directions.



9-10 		Maya Gokhale, Introduction to Reconfigurable Computing 

10-10:30	Reid Porter, et. al. A Reconfigurable Computing
		Framework for Multi-scale Cellular Image Processing

10:30-11	Break

11-11:30	Daniel G. Chavarra, Miranda and David Chassin 
		A Hardware-Accelerated Steady-State Power Flow Solver

11:30-12	Chuan He, Guan Qinand and  Wei Zhao, 
		High-order Finite Difference Seismic Modeling on 
		Reconfigurable Computing Platform

12-12:30	Zachary K. Baker and Viktor K. Prasanna, 
		Hardware Accelerated Apriori Algorithm for Data Mining

12:30-2		Lunch (on your own)

2-2:30		Chen Chang, John Wawrzynek, Robert W. Brodersen, 
		The Design And Application of BEE2 
		A High-End Reconfigurable Computing System


2:30-3		Keith D. Underwood and K. Scott Hemmert, 
		Implications of FPGAs for Floating-Point HPC Systems

3-3:30		Justin L. Tripp et. al. , Trident: An FPGA Compiler 
		Framework for Scientific Computing

3:30-4		Break

4-4:30	        Heather Quinn, et. al.
                Terrestrial-based Radiation Upsets: A Cautionary Tale

4:30-5		Prasanna Sundararajan, Xilinx,
		Future Architectures and Tools

5-5:30		Concluding Remarks, Wrap-Up